1. Field of the Invention
This invention relates to semiconductor memories and, more particularly, to improvement of the tunneling efficiency of nonvolatile semiconductor memories.
2. Description of the prior art
FIG. 1A illustrates a schematic sectional view of a memory cell 1 of a prior art semiconductor memory (Yatsuda et al., "An advanced MNOS memory device for highly-integrated byte-erasable 5V-only EEPROMs", IEDM, 1982, p.734).
The manufacturing process of the memory cell 1 having the structure shown in FIG. 1A will now be described with reference to FIGS. 2 and 3.
In an n-type silicon substrate 24, a p-type well layer 15 is formed by ion implantation (FIG. 2A). On the surface, a silicon dioxide layer 7a is formed by thermal oxidization. Then a reduced pressure SiN (nitride) film 5a is deposited by a reduced pressure CVD (LPCVD) process (FIG. 2B). The reduced pressure SiN film 5a is then selectively etched away to leave only a portion of it above a portion of the p-well 15 which will eventually form a channel region (hereafter referred to as the eventual channel region, FIG. 2C). Thermal oxidation is performed again, and then an n.sup.- type layer, comprised of segments 9a and 11a, is formed by ion implantation and thermal diffusion (FIG. 2D). The remaining reduced pressure SiN film 5a and a portion thereunder of the silicon dioxide film 7a are etched away by dipping them in a wet etching solution (FIG. 2E). Next, on the eventual channel region, an Ultra Thin Oxide film (hereafter UTO) 7 is formed by thermal oxidization, and then a reduced pressure SiN film 5 is deposited on the UTO 7 and the silicon dioxide layers 7a by the reduced pressure CVD process. Then, a polysilicon film 3 is grown on the film 5 by the CVD process (FIG. 3F). The polysilicon film 3 and reduced pressure SiN film 5 are selectively etched away using a resist mask (FIG. 3G). Then, an n.sup.+ type layers 9b and 11b (see FIG. 1A) are formed by ion implantation and thermal diffusion. Meanwhile, the eventual channel means a region 13 between a drain layer 9a, 9b and a source layer 11a, 11b.
The above memory cell 1 can be in one of two different states: an information "1" state, in which electrons are trapped in the SiN film 5; and an information "0" state, in which no electrons are trapped in the SiN film 5. To explain two states, the hysteresis loop of the memory cell 1 is shown in FIG. 1B. The horizontal axis in FIG. 1B represents gate voltage V.sub.g and the vertical axis represents threshold voltage V.sub.th. The gate voltage V.sub.g is a voltage applied to the gate electrode of the memory cell. The threshold voltage V.sub.th is a gate voltage at which a current begins to flow between the source and the drain when the voltage applied to the gate electrode is made to increase. In this case, the threshold voltage V.sub.th is given by ##EQU1## where .epsilon. is silicon dielectric constant, N.sub.A is the concentration of impurities within the substrate, V.sub.FB is the flat band voltage, C is the capacity of the gate insulating film, q is the quantity of electron charge, and .phi.F is the Fermi level (i.e. the potential of an intrinsic semiconductor from Fermi level).
In the initial state of the memory cell 1, no electrons are trapped in the SiN film 5. In this state, by applying a high voltage of about 20 V (not shown) to the gate electrode 3 of the memory cell 1, an electric field is set up between the gate electrode 3 and channel region 13. At this time, electrons in the channel region 13 are pulled by the electric field and acquire high energy, and some electrons tunnel through the silicon dioxide film 7 and enter and are trapped within the SiN film 5. This means that information "1" is written in the memory cell 1. Such a change causes the threshold voltage to increase up to the positive (see P1 in FIG. 1B). This means that the memory cell 1 has been made to serve as an enhancement mode transistor having a threshold voltage of the positive. In addition, the threshold voltage will remain as it is even if the gate voltage is cut off (see Q1 in FIG. 1B).
On the other hand, to erase the information "1", it is necessary to let the trapped electrons return to the channel region 13. This is effected by generating an electric field of the opposite polarity to that produced when writing information, by applying a high voltage of about 25 V to the channel region 13. The result after erasing the information "1" is a state in which information "0" is written. Such a change causes the threshold voltage to change from the positive to the negative (see R1 in FIG. 1B). This means that the memory cell 1 has been made to serve as a depression mode transistor having a threshold voltage of the negative. In addition, the threshold voltage will remain as it is even if the gate voltage is cut off (see S1 in FIG. 1B).
When reading out information, a judgement as to whether the written information is "0" or "1" can be made by checking whether a current flows through the channel region 13 when approximately 5 V is applied between the source 11a, 11b and drain 9a, 9b of the memory cell 1.
More specifically, when information "0" is written (i.e., when no electrons are trapped in the SiN film 5), the memory cell 1 is a depletion mode transistor, and the channel region 13 is thus energized. In this state, current flows through the channel region 13. When information "1" is stored (i.e., when electrons are trapped in the SiN film 5), the memory cell 1 is an enhancement mode transistor, and the channel region 13 is not energized. Hence, no current flows through the channel region 13.
As shown above, with respect to the memory cell 1, writing or erasing information requires application of a high voltage of 20 to 25 V. Therefore, the memory cell 1 has a high breakdown voltage structure, as shown in FIG. 1A.
The prior art semiconductor memory employing this memory cell 1 has the following problems.
Writing information "1" to the memory cell 1 (i.e., injection of electrons into the SiN film 5 for trapping) or erasing information requires application of the high voltage to the gate electrode 3.
With the application of the high voltage to the gate electrode 3, excessive stress is placed on the silicon dioxide film 7 and its reliability is reduced. Therefore, the memory cell 1 required the high breakdown voltage structure. The high breakdown voltage structure inhibits increase of integration density due to the large size of the memory cell 1, as shown in FIG. 1A. Further, the manufacturing process of the memory cell 1 with the high breakdown voltage structure is complicated (see FIG. 2), thus posing problems in connection with manufacturing efficiency.